Heterojunction bipolar transistors (HBT) are used in SiGe technologies due to their high performance (Ft, Fmax) and capabilities of driving high currents. However, SiGe HBTs have scaled poorly with newer generations, due to degradation in maximum allowed current density in the Cu wiring (i.e., electromigration limits), which require the use of multiple levels of wide wires. SiGe HBT performance is also limited by the maximum current flow out of the emitter and collector.
Solutions to the electromigration issues have given rise, though, to other issues such as, for example, poor Time-Dependent Dielectric Breakdown (TDDB) lifetime, wire RC variability, and poor yield. For example, in known solutions, wiring is provided to the emitter through M1-M2 and the collector (and base) through M1, with wide wires fanning out. These types of layouts add extra contact area in which known problems can be exacerbated by self-heating and extreme use conditions of SiGe HBT chips (i.e., need to support >125° C.). In other solutions, the HBT is widened to allow for more CABAR (ContAct BAR) or card enable signal CE (bar); however, widening the HBT increases the footprint and chip cost, and also degrades device performance. Also, known solutions cause TDDB reliability problems in minimum spaces wires or in chips with large areas. Other solutions increase wire resistance (e.g., about 2× for 90 nm M1) and wire resistance variability.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.